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MMX technology Data Types
MMX ¤Þ¤J¤F¥H¤U´XºØ·sªº¸ê®Æ§ÎºA : Packed byte, packed word, packed doubleword, Packed
Quadword
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Packed byte : ±N
8 Ó byte ¦X¦¨¤@Ó
64 bits,
Packet word : ±N
4 Ó word ¦X¦¨¤@Ó
64 bits,
Packet doubleword : ±N
2 Ó word ¦X¦¨¤@Ó
64 bits,
Packet quadword : ¤@Ó
64 bits
¤j³¡¥÷ªº¦h´CÅéÀ³¥Îµ{¦¡³£¨Ï¥Î 8
bits ©Î 16 bits ªº¸ê®Æ,
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64 bits ¤F, ¦pªG¤@¦¸¥u¶Ç 8 or 6 bits, ·|³y¦¨
bandwidth ªº®ö¶O, ¦]¦¹, ±Nµuªº¸ê®Æ¥]¦b¤@°_, ¤@¦¸¶Ç°e64Ó bits, ¥i¥H
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MMX instruction set Feature
saturation arithmetic
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bit ¥á±ó, ¦]¦¹·|¦³¨â¼Æ¬Û¥[²£¥Íªºµ²ªG¤ñ³o¨âӼƳ£ÁÙn¤pªº±¡§Î¡C¦b¦h´CÅ骺À³¥Îµ{¦¡¤¤¡A±`±`·|¦³ºñ¦â¥[ºñ¦â³o¤@Ãþªº¹Bºâ¡Cºñ¦â¥[ºñ¦â¡A§Ú̹w´Á¥L·|Åܦ¨²`ºñ¦â¡A©ÎªÌ²`¨ìÅܦ¨¶Â¦â¡C¦ý¬On¬Oµo¥Í
overflow ¡A´N¤@¤Á³£ÅܼˤF¡A¥¦¥i¯àÅܦ¨«Ü©_©ÇªºÃC¦â¡CMMX ´£¨Ñ¤@ºØ
saturation arithmetic,¨Ï±oºñ¦â¥[ºñ¦â³Ì¦h¬OÅܦ¨¶Â¦â¡A¦Ó¤£·|ÅÜ¥X¤°»ò©_©ÇªºÃC¦â¡C
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parallelism
MMX ´£¨Ñ¤FÃþ¦ü
SIMD ªº¤è¦¡, ¥i¥H¤@¦¸¹ï¦hÓ
operand °µ¬Û¦Pªº¹Bºâ¡C¤ñ¦p»¡¦V¶q(x1,y1,z1) ©M¦V¶q
(x2,y2,z2) ªº¦V¶q¥[ªk¥i¥H¤@¦¸§¹¦¨¡C¹ï¦h´CÅéÀ³¥Îµ{¦¡¨¥, kernel
ªº³¡¥÷´X¥G³£¬O¥i¥H¥¦æ³B²zªº data ¡C³o¤]¬O
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Table 1. Summary of the MMX instruction
set
Opcode |
Options |
Description |
Padd[b/w/d]
Psub[b/w/d] |
Wrap
around and saturate |
Paralle
Add and subtract of packed eight bytes, four 16-bit words, or
two 32-bit doubleworlds. |
Pcmped[b/w/d]
Pcmpgt[b/w/d] |
Equal
or greater than |
Parallel
Compare of eight bytes, four 16-bit words, or two 32-bit double-words.
Result is mask of 1s if true or 0s if false. |
Pmullw
Pmulhw |
Result
is high or low order bits. |
Parallel
Multiply of four signed 16-bit words. Low-order or high-order
16-bits of the 32-bit result are chosen. |
Psra[w/d]
Psll[w/d/q] Psrl[w/d/q] |
Shift
count in register or immediate |
Parallel
Shift of 4 words, 2 double-words, or the full 64 bits are shifted
arithmetic right,logical right and left. |
Punpkl[bw/wd/dq] Punpckh[bw/wd/dq] |
|
Parallel
Unpacking(interleaved merge) of eight bytes, four 16-bit words,
or two 32-bit doublewords. |
Packss[wb/dw] |
Always
saturate |
Parallel
Packing of doublewords to words or words to bytes. |
Pand
Pandn Por Pxor |
|
64-bit
bitwise logical operations |
Mov[d/q] |
|
Moves
32 or 64 bits to and from memory to MMX registers or between
MMX registers. 32-bits can be moved between MMX and integer
register. |
Emms |
|
Empty
FP registers tag bits. |
Á`¦@¦³ 57 Ó instruction
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MMX ªº¬Û®e©Ê
MMX µo®iªº¥Dn¥Ø¼Ð¤§¤@´N¬On¯à°÷»P²{¦³ªº
Intel CPU ¬[ºcµ²¦X¡A¦Ó즳ªº³nÅ餣»Ýn«·s½sͤ]¥i¥H¦b¦³ MMX
ªº CPU
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no more register
²Ä¤@Ón¦Ò¼{ªº´N¬O :
¤£¯à¤Þ¤J·sªº register ¥H¤Î·sªºª¬ºA(condition
code)¡C¦b¦h¤uªºÀô¹Ò¤U, ¨C¦¸ context switch ®É, OS ·|«O¦s¨CÓ
process ªº©Ò¦³ª¬ºA¡C¦pªG¥[¤J·sªº register, ¤]´N¬O»¡
OS ¥²¶·ª¾¹D¦³³oÓ register¡C¦ý¬O³o¼Ëªº¸Ü, ²{¦³ªº OS ´N¤£¯àª½±µ¦b
MMX ¤W¶]¤F¡C©Ò¥H, ¤£¯à°÷¤Þ¤J·sªº
register ¡C¨º, MMX ¥ÎþÓ register ?
MMX ªº¸ê®Æ³£¥]¦¨
64 bit ¤@²Õ¤F, ¦Ó²{¦³ªº Pentium
µ¥ CPU ªº register ³£ÁÙ¬O 32 bit ªº,
¤]¦]¬°¦p¦¹, ¦]¦¹, MMX ¨Ï¥Î 80bit ªº Floating-point
register §@¬°¥¦ªº¼È¦s¾¹¡A·í floating point register
¤¤¦s©ñªº¬OMMX ªº packet data, ¶W¹L²Ä 63 Ó bit ¥H¤Wªº¦ì¤¸³£³]¦¨ 1, ¦pªG§â³o¦ê 01 ¸ÑÄÀ¦¨
floating point , ·|±o¨ì¤@Ó NAN(not a number)¡CÀ³¥Îµ{¦¡¤£¯à¦b¥Î floating-point unit
°µ¯BÂI¹Bºâ®É¤S¨Ï¥Î MMX ªº«ü¥O¡C
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°Ñ¦Ò¸ê®Æ :
Intel MMX for Multimedia
PC : COMMUNICATIONS OF THE ACM Jan. 1997/Vol. 40 No.1
MMX Technology Extension
To The Intel Architecture : IEEE Micro Aug. 1996
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